Abstract

An 8-bit array multiplier can multiply two 8-bit numbers and produce a 16-bit output. In the final project for EE103 (Introduction to VLSI Design), a low power, parity check and zero flag, 8-bit array multiplier will be designed and simulated using Cadence. Circuit optimization strategies will be applied to reduce power consumption, such as custom design logic function, transistor sizing, and parasitic capacitance minimization. The worst-case propagation delay and average power consumption results are presented and compared with a gate level CMOS multiplier design.