Quantitative Performance Results

Best & Worst Cases
CMOS Implementation

Best Case Rise Time	Best Case Fall Time	Worst Case Rise Time	Worst Case Fall Time
14.6 ns	9.8 ns	15.4 ns	6.5 ns

 

Final Project Results
Schematic

Best Case Rise Time	Best Case Fall Time	Worst Case Rise Time	Worst Case Fall Time
11.3 ns	6.2 ns	16.8 ns	10.4 ns

Extracted

Best Case Rise Time	Best Case Fall Time	Worst Case Rise Time	Worst Case Fall Time
6.8 ns	4.1 ns	8.9 ns	7.3 ns

Best case is the delay for P0 because it is the output with the shortest path. Worst Case is P15 because it is the output that has the longest path.

Lower Power
In the original design of the multiplier, 2688 transistors were used. In the final design, 2176 transistors were used. The number of transistors reduced is 512 and percentage difference is 21%.

Parity Check and Zero Detect
Parity check and zero detect were integrated into the design. Parity check is operated on input A. Parity check is ‘0’ when there is an even number of 1’s and is ‘1’ when there is an odd number of 1’s. Zero detect is ‘0’ when the product is ‘0000 0000 0000 0000’ and ‘1’ when the product is not zero.