Pseudo nMOS Array Multiplier

EE103 VLSI Final Project

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Abstract
Conclusion
Design Strategy
Progress
Quantitative Performance Results
Sub-Cells
Table of Completion
Top-Level Block Diagram

Parity Check

Schematic

Symbol

Functional

Layout

Extracted

LVS

Schematic Simulation

Post-Layout (Extracted) Simulation

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December 7, 2014alice

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