| Gate | Functional | Func. Sim | Schematic | Spectre Sim | Layout | DRC | LVS | Post-Layout Sim |
|---|---|---|---|---|---|---|---|---|
| Inverter | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| NAND2 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| NAND4 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| NOR4 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Half Adder Cell | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Full Adder Cell | 0 | 0 | 3 | 3 | 3 | 3 | 3 | 3 |
| XOR2 | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Zero Detector | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Parity Check | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Array Multiplier | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
| Multiplier w/ Added Functionality | 3 | 3 | 3 | 3 | 3 | 3 | 3 | 3 |
Alice Lee: Half Adder Cell, Zero Detect, Parity, Initial Layout
Nicholas Andre: Full Adder Cell, Interconnects and routing
Testing and troubleshooting of the overall block will be done together.
1 – Implemented but not verified // 2 – Does not work as planned // 3 – Works as designed
Pseudo nMOS Array Multiplier 